diff options
| author | Kenneth Graunke <[email protected]> | 2015-09-29 14:32:02 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2015-10-21 14:27:46 -0700 |
| commit | ac98888afdc121e6eaafc9c5393647a2df4baef6 (patch) | |
| tree | 180d105faf6ad922d5d41cac91266d7bd4360b43 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | bea75227829512ab0e4766e00ac1b509c7586667 (diff) | |
i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode.
In scalar mode, geometry shader inputs can easily take up hundreds of
registers. This makes pushing VUE entries impractical; we'll need to
resort to the pull model in some cases.
To support this, we introduce a new opcode corresponding to the "URB
Read SIMD8" message.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Kristian Høgsberg <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index b2ce197faba..bd7d0b1c9a7 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1031,6 +1031,15 @@ enum opcode { SHADER_OPCODE_GEN4_SCRATCH_WRITE, SHADER_OPCODE_GEN7_SCRATCH_READ, + /** + * Gen8+ SIMD8 URB Read message. + * + * Source 0: The header register, containing URB handles (g1). + * + * Currently only supports constant offsets, in inst->offset. + */ + SHADER_OPCODE_URB_READ_SIMD8, + SHADER_OPCODE_URB_WRITE_SIMD8, SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT, SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, |