From ac98888afdc121e6eaafc9c5393647a2df4baef6 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 29 Sep 2015 14:32:02 -0700 Subject: i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In scalar mode, geometry shader inputs can easily take up hundreds of registers. This makes pushing VUE entries impractical; we'll need to resort to the pull model in some cases. To support this, we introduce a new opcode corresponding to the "URB Read SIMD8" message. Signed-off-by: Kenneth Graunke Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_defines.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mesa/drivers/dri/i965/brw_defines.h') diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index b2ce197faba..bd7d0b1c9a7 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1031,6 +1031,15 @@ enum opcode { SHADER_OPCODE_GEN4_SCRATCH_WRITE, SHADER_OPCODE_GEN7_SCRATCH_READ, + /** + * Gen8+ SIMD8 URB Read message. + * + * Source 0: The header register, containing URB handles (g1). + * + * Currently only supports constant offsets, in inst->offset. + */ + SHADER_OPCODE_URB_READ_SIMD8, + SHADER_OPCODE_URB_WRITE_SIMD8, SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT, SHADER_OPCODE_URB_WRITE_SIMD8_MASKED, -- cgit v1.2.3