Revert recent changes about not including compute in combined limits.

As far as I can tell, no one reviewed these changes, they made i965
assert fail on driver load, and I am not certain they are correct.
(Hopefully reverting these does not break radeonsi too badly...)

The uniform related changes seem fine and reasonable, but the texture
image units change is possibly incorrect.  According to the
OES_tessellation_shader spec issue 5:

   (5) How are aggregate shader limits computed?

    RESOLVED: Following the GL 4.4 model, but we restrict uniform
    buffer bindings to 12/stage instead of 14, this results in

        MAX_UNIFORM_BUFFER_BINDINGS = 72
            This is 12 bindings/stage * 6 shader stages, allowing a static
            partitioning of the bindings even though at most 5 stages can
            appear in a program object).
        MAX_COMBINED_UNIFORM_BLOCKS = 60
            This is 12 blocks/stage * 5 stages, since compute shaders can't
            be mixed with other stages.
        MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96
            This is 16 textures/stage * 6 stages.

which definitely is including compute shaders in that last limit.
Not including compute shaders breaks the following test:
dEQP-GLES31.functional.state_query.integer.max_combined_texture_image_units_getinteger

There was enough breakage that I figured we should just send this back
to the drawing board.

Revert "i965: don't include compute resources in "Combined" limits"
Revert "st/mesa: don't include compute resources in "Combined" limits"
Revert "mesa: don't include compute resources in MAX_COMBINED_* limits"

This reverts commit b03dcb1e5f507c5950d0de053a6f76e6306ee71f.
This reverts commit cff290df4c09547cd2cb3b129ec59bdebdadba90.
This reverts commit 45f87a48f94148b484961f18a4f1ccf86f066b1c.

1 files changed, 11 insertions, 11 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 59871ed84e2..6ba64e4e06d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -421,10 +421,10 @@ brw_initialize_context_constants(struct brw_context *brw)
           ctx->Const.MaxComputeWorkGroupSize[0] >= 128),
    };
 
-   unsigned num_gfx_stages = 0;
-   for (int i = 0; i < MESA_SHADER_COMPUTE; i++) {
+   unsigned num_stages = 0;
+   for (int i = 0; i < MESA_SHADER_STAGES; i++) {
       if (stage_exists[i])
-         num_gfx_stages++;
+         num_stages++;
    }
 
    unsigned max_samplers =
@@ -505,14 +505,14 @@ brw_initialize_context_constants(struct brw_context *brw)
       MIN2(ctx->Const.MaxTextureCoordUnits,
            ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits);
 
-   ctx->Const.MaxUniformBufferBindings = num_gfx_stages * BRW_MAX_UBO;
-   ctx->Const.MaxCombinedUniformBlocks = num_gfx_stages * BRW_MAX_UBO;
-   ctx->Const.MaxCombinedAtomicBuffers = num_gfx_stages * BRW_MAX_ABO;
-   ctx->Const.MaxCombinedShaderStorageBlocks = num_gfx_stages * BRW_MAX_SSBO;
-   ctx->Const.MaxCombinedTextureImageUnits = num_gfx_stages * max_samplers;
-   ctx->Const.MaxCombinedImageUniforms = num_gfx_stages * BRW_MAX_IMAGES;
-   ctx->Const.MaxShaderStorageBufferBindings =
-      (num_gfx_stages + stage_exists[MESA_SHADER_COMPUTE]) * BRW_MAX_SSBO;
+   ctx->Const.MaxUniformBufferBindings = num_stages * BRW_MAX_UBO;
+   ctx->Const.MaxCombinedUniformBlocks = num_stages * BRW_MAX_UBO;
+   ctx->Const.MaxCombinedAtomicBuffers = num_stages * BRW_MAX_ABO;
+   ctx->Const.MaxCombinedShaderStorageBlocks = num_stages * BRW_MAX_SSBO;
+   ctx->Const.MaxShaderStorageBufferBindings = num_stages * BRW_MAX_SSBO;
+   ctx->Const.MaxCombinedTextureImageUnits = num_stages * max_samplers;
+   ctx->Const.MaxCombinedImageUniforms = num_stages * BRW_MAX_IMAGES;
+
 
    /* Hardware only supports a limited number of transform feedback buffers.
     * So we need to override the Mesa default (which is based only on software