diff options
| author | Chris Wilson <[email protected]> | 2015-04-30 17:04:51 +0100 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2015-06-24 10:35:04 -0700 |
| commit | 4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9 (patch) | |
| tree | 623f9d02e44c1601d8abf09fa89e7fd06186aa83 /src/mesa/drivers/dri/i965/brw_clear.c | |
| parent | 9d4b9f1e0c661e5ed8ce2e71c76ce8cc1adf90dd (diff) | |
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_clear.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clear.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 1d4ba3cac7e..f981388ef1a 100644 --- a/src/mesa/drivers/dri/i965/brw_clear.c +++ b/src/mesa/drivers/dri/i965/brw_clear.c @@ -184,7 +184,7 @@ brw_fast_clear_depth(struct gl_context *ctx) * must be issued before the rectangle primitive used for the depth * buffer clear operation. */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); if (fb->MaxNumLayers > 0) { for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) { @@ -204,7 +204,7 @@ brw_fast_clear_depth(struct gl_context *ctx) * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then * followed by Depth FLUSH' */ - intel_batchbuffer_emit_mi_flush(brw); + brw_emit_mi_flush(brw); } /* Now, the HiZ buffer contains data that needs to be resolved to the depth |