i965/msaa: Add an enum to describe MSAA layout.

From the Ivy Bridge PRM, Vol 1 Part 1, p112:

    There are three types of multisampled surface layouts designated
    as follows:
      - IMS Interleaved Multisampled Surface
      - CMS Compressed Mulitsampled Surface
      - UMS Uncompressed Multisampled Surface

Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved.  To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}.  It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM.  CMS layout is not yet used.

The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.

Reviewed-by: Chad Versace <[email protected]>

1 files changed, 15 insertions, 17 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index cc7e12e1ae7..053eef74071 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -97,6 +97,12 @@ void set(struct brw_context *brw,
     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
     */
    uint32_t brw_surfaceformat;
+
+   /**
+    * For MSAA surfaces, MSAA layout that should be used when setting up the
+    * surface state for this surface.
+    */
+   intel_msaa_layout msaa_layout;
 };
 
 
@@ -192,38 +198,30 @@ struct brw_blorp_blit_prog_key
     */
    unsigned tex_samples;
 
-   /* If tex_samples > 0, this boolean indicates whether or not the GPU
-    * pipeline will be configured to read from it as though it were an
-    * interleaved MSAA layout.  False if tex_samples == 0.
+   /* MSAA layout that has been configured in the surface state for texturing
+    * from.
     */
-   bool tex_interleaved;
+   intel_msaa_layout tex_layout;
 
    /* Actual number of samples per pixel in the source image. */
    unsigned src_samples;
 
-   /* If src_samples > 0, this boolean indicates whether or not the source
-    * image uses an interleaved MSAA layout.  False if src_samples == 0.
-    */
-   bool src_interleaved;
+   /* Actual MSAA layout used by the source image. */
+   intel_msaa_layout src_layout;
 
    /* Number of samples per pixel that have been configured in the render
     * target.
     */
    unsigned rt_samples;
 
-   /* If rt_samples > 0, whether or not the GPU pipeline will be configured
-    * to write to it as though it were an interleaved MSAA layout.  False if
-    * rt_samples == 0.
-    */
-   bool rt_interleaved;
+   /* MSAA layout that has been configured in the render target. */
+   intel_msaa_layout rt_layout;
 
    /* Actual number of samples per pixel in the destination image. */
    unsigned dst_samples;
 
-   /* If dst_samples > 0, whether or not the destination image uses an
-    * interleaved MSAA layout.  False if dst_samples == 0.
-    */
-   bool dst_interleaved;
+   /* Actual MSAA layout used by the destination image. */
+   intel_msaa_layout dst_layout;
 
    /* True if the source image is W tiled.  If true, the surface state for the
     * source image must be configured as Y tiled, and tex_samples must be 0.