diff options
| author | Scott D Phillips <[email protected]> | 2018-04-30 10:25:48 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2018-05-25 11:05:46 -0700 |
| commit | d21c086d819d78fb3f6abcbb14aa492970f442aa (patch) | |
| tree | a4d98307cb9590a10c5938ac21793f57dd43b1d6 /src/mesa/drivers/dri/i965/Makefile.sources | |
| parent | fb20ae0374425ae3aff2a50a498c7e2b428632a4 (diff) | |
i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear
The reference for MOVNTDQA says:
For WC memory type, the nontemporal hint may be implemented by
loading a temporary internal buffer with the equivalent of an
aligned cache line without filling this data to the cache.
[...] Subsequent MOVNTDQA reads to unread portions of the WC
cache line will receive data from the temporary internal
buffer if data is available.
This hidden cache line sized temporary buffer can improve the
read performance from wc maps.
v2: Add mfence at start of tiled_to_linear for streaming loads (Chris)
Reviewed-by: Chris Wilson <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Acked-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa/drivers/dri/i965/Makefile.sources')
| -rw-r--r-- | src/mesa/drivers/dri/i965/Makefile.sources | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index db6591ab90a..ce7633c53c4 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -110,11 +110,13 @@ i965_FILES = \ intel_tex_image.c \ intel_tex_obj.h \ intel_tex_validate.c \ - intel_tiled_memcpy.c \ - intel_tiled_memcpy.h \ intel_upload.c \ libdrm_macros.h +intel_tiled_memcpy_FILES = \ + intel_tiled_memcpy.c \ + intel_tiled_memcpy.h + i965_gen4_FILES = \ genX_blorp_exec.c \ genX_state_upload.c |