From d21c086d819d78fb3f6abcbb14aa492970f442aa Mon Sep 17 00:00:00 2001 From: Scott D Phillips Date: Mon, 30 Apr 2018 10:25:48 -0700 Subject: i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear The reference for MOVNTDQA says: For WC memory type, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an aligned cache line without filling this data to the cache. [...] Subsequent MOVNTDQA reads to unread portions of the WC cache line will receive data from the temporary internal buffer if data is available. This hidden cache line sized temporary buffer can improve the read performance from wc maps. v2: Add mfence at start of tiled_to_linear for streaming loads (Chris) Reviewed-by: Chris Wilson Reviewed-by: Matt Turner Acked-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/Makefile.sources | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965/Makefile.sources') diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources index db6591ab90a..ce7633c53c4 100644 --- a/src/mesa/drivers/dri/i965/Makefile.sources +++ b/src/mesa/drivers/dri/i965/Makefile.sources @@ -110,11 +110,13 @@ i965_FILES = \ intel_tex_image.c \ intel_tex_obj.h \ intel_tex_validate.c \ - intel_tiled_memcpy.c \ - intel_tiled_memcpy.h \ intel_upload.c \ libdrm_macros.h +intel_tiled_memcpy_FILES = \ + intel_tiled_memcpy.c \ + intel_tiled_memcpy.h + i965_gen4_FILES = \ genX_blorp_exec.c \ genX_state_upload.c -- cgit v1.2.3