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authorBen Widawsky <[email protected]>2015-04-14 14:57:51 -0700
committerBen Widawsky <[email protected]>2015-11-20 11:45:32 -0800
commitd23aa634e0d45bbeda0f48033cc42656259ce0ef (patch)
tree7d9dcb5cb4c7e6db5537695710797b230f2f9c39 /src/mesa/drivers/dri/common/xmlpool.h
parent2f7d2fd9979ce111af9c3a79b967d4efc029ab60 (diff)
i965/skl: Add fast color clear infrastructure
Patch was originally called: i965/skl: Enable fast color clears on SKL Skylake introduces some differences in the way that fast clears are programmed and in the restrictions for using fast clears. Since some of these are non-obvious, and fast clears are currently disabled globally, we can enable the simple stuff here and leave the weirder stuff and separately reviewable work. Based on a patch originally from Kristian. Note that within this patch the change in scaling factors could be achieved with this hunk instead. I've opted to keep things more like how the docs describe it however. --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -150,9 +150,13 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw, /* In release builds, fall through */ case I915_TILING_Y: *width_px = 32 / mt->cpp; - *height = 4; + if (brw->gen >= 9) + *height = 2; + else + *height = 4; v2: Add braces for the multiline (Matt + Chad) Comment updates (requested by Chad) Modified commit message Commit message from Chad explaining the MCS height change (Chad) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Neil Roberts <[email protected]> Reviewed-by: Chad Versace <[email protected]>
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