diff options
| author | Marek Olšák <[email protected]> | 2019-11-07 16:53:58 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-11-19 18:20:05 -0500 |
| commit | ebe757965567c85286245f82ba5b8f90804da19a (patch) | |
| tree | af76883208d4ff9f1dbcbd2ca471711922ffce0e /src/intel | |
| parent | 3a8d6868897c7dfe72bac09c1eddd551144ca751 (diff) | |
nir: move data.image.access to data.access
The size of the data structure doesn't change.
Reviewed-by: Connor Abbott <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_nir_lower_image_load_store.c | 4 | ||||
| -rw-r--r-- | src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_nir_lower_image_load_store.c b/src/intel/compiler/brw_nir_lower_image_load_store.c index b54cf32f443..a0a7cd8b06a 100644 --- a/src/intel/compiler/brw_nir_lower_image_load_store.c +++ b/src/intel/compiler/brw_nir_lower_image_load_store.c @@ -583,7 +583,7 @@ lower_image_store_instr(nir_builder *b, /* For write-only surfaces, we trust that the hardware can just do the * conversion for us. */ - if (var->data.image.access & ACCESS_NON_READABLE) + if (var->data.access & ACCESS_NON_READABLE) return false; const enum isl_format image_fmt = @@ -696,7 +696,7 @@ lower_image_size_instr(nir_builder *b, /* For write-only images, we have an actual image surface so we fall back * and let the back-end emit a TXS for this. */ - if (var->data.image.access & ACCESS_NON_READABLE) + if (var->data.access & ACCESS_NON_READABLE) return false; /* If we have a matching typed format, then we have an actual image surface diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index f37b672543b..3fdc3520025 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -752,7 +752,7 @@ lower_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(desc)); } else if (binding_offset > MAX_BINDING_TABLE_SIZE) { const bool write_only = - (var->data.image.access & ACCESS_NON_READABLE) != 0; + (var->data.access & ACCESS_NON_READABLE) != 0; nir_ssa_def *desc = build_descriptor_load(deref, 0, 2, 32, state); nir_ssa_def *handle = nir_channel(b, desc, write_only ? 1 : 0); @@ -1321,7 +1321,7 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice, /* NOTE: This is a uint8_t so we really do need to != 0 here */ pipe_binding[i].write_only = - (var->data.image.access & ACCESS_NON_READABLE) != 0; + (var->data.access & ACCESS_NON_READABLE) != 0; } } |