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authorJason Ekstrand <[email protected]>2017-04-05 16:59:06 -0700
committerJason Ekstrand <[email protected]>2017-04-10 07:57:21 -0700
commitd3785dcb2f65771f32ee32532fc4ff5c1aa3e952 (patch)
tree2c93695ab0123f72797f52b922191dc946d41e84 /src/intel
parentf93dc5beeed8076254998b713dde2b2211bda3b8 (diff)
intel/blorp: Emit 3DSTATE_STENCIL_BUFFER before HIER_DEPTH
We're about to replace blorp's emit code with ISL and it emits them in the other order. This makes diffing the aubs easier. Reviewed-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/blorp/blorp_genX_exec.h24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 379146245d9..9532e89b12f 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -854,18 +854,6 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
}
}
- blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) {
- if (params->depth.aux_usage == ISL_AUX_USAGE_HIZ) {
- hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1;
- hiz.SurfaceBaseAddress = params->depth.aux_addr;
- hiz.HierarchicalDepthBufferMOCS = mocs;
-#if GEN_GEN >= 8
- hiz.SurfaceQPitch =
- isl_surf_get_array_pitch_sa_rows(&params->depth.aux_surf) >> 2;
-#endif
- }
- }
-
blorp_emit(batch, GENX(3DSTATE_STENCIL_BUFFER), sb) {
if (params->stencil.enabled) {
#if GEN_GEN >= 8 || GEN_IS_HASWELL
@@ -883,6 +871,18 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
}
}
+ blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) {
+ if (params->depth.aux_usage == ISL_AUX_USAGE_HIZ) {
+ hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1;
+ hiz.SurfaceBaseAddress = params->depth.aux_addr;
+ hiz.HierarchicalDepthBufferMOCS = mocs;
+#if GEN_GEN >= 8
+ hiz.SurfaceQPitch =
+ isl_surf_get_array_pitch_sa_rows(&params->depth.aux_surf) >> 2;
+#endif
+ }
+ }
+
/* 3DSTATE_CLEAR_PARAMS
*
* From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS: