diff options
author | Jason Ekstrand <[email protected]> | 2020-01-22 22:37:10 -0600 |
---|---|---|
committer | Marge Bot <[email protected]> | 2020-01-24 19:18:26 +0000 |
commit | c70a786c77370bbc47f71a9f529d50116fd511da (patch) | |
tree | 1e2202f681fc20948b02f1583aa3e2d974dea182 /src/intel | |
parent | e39c52787e89225343032fecd628988f39d9b442 (diff) |
anv: Improve BTI change cache flushing
This commit makes two changes:
1. We set pending_pipe_bits instead of emitting PIPE_CONTROL directly
for the flush at the end of cmd_buffer_begin_subpass.
2. Because BLORP ops such as vkCmdClearAttachments may come in the
middle of a render pass, we have to also flag the need for a cache
flush after the blorp op.
Fixes: 185630c6bc97 "anv/blorp: Do the gen11 BTI flush"
Reviewed-by: Kenneth Graunke <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3547>
Diffstat (limited to 'src/intel')
-rw-r--r-- | src/intel/vulkan/genX_blorp_exec.c | 14 | ||||
-rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 10 |
2 files changed, 17 insertions, 7 deletions
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index 302acb54461..fed4455ca07 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -272,6 +272,20 @@ genX(blorp_exec)(struct blorp_batch *batch, blorp_exec(batch, params); +#if GEN_GEN >= 11 + /* The PIPE_CONTROL command description says: + * + * "Whenever a Binding Table Index (BTI) used by a Render Taget Message + * points to a different RENDER_SURFACE_STATE, SW must issue a Render + * Target Cache Flush by enabling this bit. When render target flush + * is set due to new association of BTI, PS Scoreboard Stall bit must + * be set in this packet." + */ + cmd_buffer->state.pending_pipe_bits |= + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STALL_AT_SCOREBOARD_BIT; +#endif + cmd_buffer->state.gfx.vb_dirty = ~0; cmd_buffer->state.gfx.dirty = ~0; cmd_buffer->state.push_constants_dirty = ~0; diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index c8ec8697b95..6fabe9134a3 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -4910,13 +4910,9 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, * is set due to new association of BTI, PS Scoreboard Stall bit must * be set in this packet." */ - anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { - pc.RenderTargetCacheFlushEnable = true; - pc.StallAtPixelScoreboard = true; -#if GEN_GEN >= 12 - pc.TileCacheFlushEnable = true; -#endif - } + cmd_buffer->state.pending_pipe_bits |= + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STALL_AT_SCOREBOARD_BIT; #endif } |