diff options
author | Jason Ekstrand <[email protected]> | 2020-03-04 14:37:03 -0600 |
---|---|---|
committer | Marge Bot <[email protected]> | 2020-03-19 20:54:19 +0000 |
commit | 9dbff6f6ce0dea622f98c9d14336148e9afc19ae (patch) | |
tree | 7d1d356ebfd66eb8f348f9e6d0710202c7ef0758 /src/intel | |
parent | 507abc395940debf59df19d51fdff071cdb9f6ed (diff) |
intel/iris: Always initialize CCS to 0
Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a
misunderstanding of the following lines in the bspec:
The following are the general SW requirements for MCS buffer clear
functionality:
...
- If Software wants to enable Color Compression without Fast
clear, Software needs to initialize MCS with zeros.
- Lossless compression and CCS initialized to all F (using HW
Fast Clear or SW direct Clear) on the same surface is not
supported.
The first line does not refer to the CCS as the comment author supposed
but refers to the MCS as the comment says. It means that if you want to
use MCS compression without a fast-clear, you should initialize the MCS
to 0x00. This is because the value 0x00 in the MCS means "all data is
in plane 0" which is a perfectly valid non-fast-clear initialization.
It's also the value the MCS should be in if you do a RECTLIST slow-clear
where the primitive fully covers each pixel such that the same value is
written to all samples.
The second line in the above quote seems to imply that CCS fast-clear is
incompatible with MCS fast-clear. In particular, MCS+CCS fast-clear
uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in
either the compressed or the pass-through state. Therefore, we should
initialize the CCS to 0x00 even for MCS+CCS surfaces.
Reviewed-by: Sagar Ghuge<[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
Diffstat (limited to 'src/intel')
-rw-r--r-- | src/intel/isl/isl.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 3643dab9790..f3cb1751ea9 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -645,6 +645,10 @@ enum isl_aux_usage { /** The auxiliary surface is an MCS and CCS is also enabled * + * In this mode, we have fused MCS+CCS compression where the MCS is used + * for fast-clears and "identical samples" compression just like on Gen7-11 + * but each plane is then CCS compressed. + * * @invariant isl_surf::samples > 1 */ ISL_AUX_USAGE_MCS_CCS, |