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authorJason Ekstrand <[email protected]>2018-01-26 16:22:27 -0800
committerJason Ekstrand <[email protected]>2018-01-30 17:16:33 -0800
commit97938dac36e2875001ba24a7968e4cd8e2271321 (patch)
tree35d9a3a49bf46e77e8e56196017c41cceebeffc4 /src/intel
parentee63933a73653564c490cff1f841d98e6265df97 (diff)
anv/cmd_buffer: Re-emit the pipeline at every subpass
If we ever hit this edge-case, it can theoretically cause problem for CNL because we could end up changing render targets without re-emitting 3DSTATE_MULTISAMPLE which is part of the pipeline. Just get rid of the edge case. Cc: [email protected] Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index fc1b6ffe0f5..9ad1b30bf92 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3204,6 +3204,17 @@ genX(cmd_buffer_set_subpass)(struct anv_cmd_buffer *cmd_buffer,
if (GEN_GEN == 7)
cmd_buffer->state.gfx.vb_dirty |= ~0;
+ /* It is possible to start a render pass with an old pipeline. Because the
+ * render pass and subpass index are both baked into the pipeline, this is
+ * highly unlikely. In order to do so, it requires that you have a render
+ * pass with a single subpass and that you use that render pass twice
+ * back-to-back and use the same pipeline at the start of the second render
+ * pass as at the end of the first. In order to avoid unpredictable issues
+ * with this edge case, we just dirty the pipeline at the start of every
+ * subpass.
+ */
+ cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
+
/* Perform transitions to the subpass layout before any writes have
* occurred.
*/