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authorIan Romanick <[email protected]>2018-06-26 18:30:09 -0700
committerIan Romanick <[email protected]>2018-07-06 16:20:07 -0700
commit9626ea497de8af5580ee3af76df79ad8083c5922 (patch)
treec6423437b0e8cb11634ceec8f0809a9b414fd85f /src/intel
parent88bd37c01060169b451ca2c3900830342d34a9a2 (diff)
i965/vec4: Properly handle sign(-abs(x))
This is achived by copying the sign(abs(x)) optimization from the FS backend. On Gen7 an earlier platforms, this fixes new piglit tests: - glsl-1.10/execution/vs-sign-neg-abs.shader_test - glsl-1.10/execution/vs-sign-sat-neg-abs.shader_test Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/compiler/brw_vec4_nir.cpp18
1 files changed, 17 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp
index b77fa5fa821..4c3a2d2e10a 100644
--- a/src/intel/compiler/brw_vec4_nir.cpp
+++ b/src/intel/compiler/brw_vec4_nir.cpp
@@ -1805,7 +1805,23 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
unreachable("not reached: should have been lowered");
case nir_op_fsign:
- if (type_sz(op[0].type) < 8) {
+ if (op[0].abs) {
+ /* Straightforward since the source can be assumed to be either
+ * strictly >= 0 or strictly <= 0 depending on the setting of the
+ * negate flag.
+ */
+ inst = emit(MOV(dst, op[0]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+
+ inst = (op[0].negate)
+ ? emit(MOV(dst, brw_imm_f(-1.0f)))
+ : emit(MOV(dst, brw_imm_f(1.0f)));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+
+ if (instr->dest.saturate)
+ inst->saturate = true;
+
+ } else if (type_sz(op[0].type) < 8) {
/* AND(val, 0x80000000) gives the sign bit.
*
* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not