diff options
| author | Anuj Phogat <[email protected]> | 2019-09-09 11:17:19 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2019-09-11 11:29:37 -0700 |
| commit | 729de1488f49033bc181b8123af5658228a51bf1 (patch) | |
| tree | 4772f68368c54368a605ebc59f4796570c7a27dd /src/intel | |
| parent | ee2bde5232b0b703db5482b65b42bc6cbf29bb8f (diff) | |
intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM
Initial benchmarking didn't show any performance benefits. But it might eventually.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index df76b33a7c3..06b9d497cb0 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -292,6 +292,17 @@ genX(init_device_state)(struct anv_device *device) lri.DataDWord = cache_mode_0; } } + + /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM. */ + uint32_t common_slice_chicken4; + anv_pack_struct(&common_slice_chicken4, GENX(COMMON_SLICE_CHICKEN4), + .EnableHardwareFilteringinWM = true, + .EnableHardwareFilteringinWMMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN4_num); + lri.DataDWord = common_slice_chicken4; + } #endif /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so |