From 729de1488f49033bc181b8123af5658228a51bf1 Mon Sep 17 00:00:00 2001 From: Anuj Phogat Date: Mon, 9 Sep 2019 11:17:19 -0700 Subject: intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM Initial benchmarking didn't show any performance benefits. But it might eventually. Signed-off-by: Anuj Phogat Reviewed-by: Kenneth Graunke --- src/intel/vulkan/genX_state.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/intel') diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index df76b33a7c3..06b9d497cb0 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -292,6 +292,17 @@ genX(init_device_state)(struct anv_device *device) lri.DataDWord = cache_mode_0; } } + + /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM. */ + uint32_t common_slice_chicken4; + anv_pack_struct(&common_slice_chicken4, GENX(COMMON_SLICE_CHICKEN4), + .EnableHardwareFilteringinWM = true, + .EnableHardwareFilteringinWMMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN4_num); + lri.DataDWord = common_slice_chicken4; + } #endif /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so -- cgit v1.2.3