diff options
| author | Lionel Landwerlin <[email protected]> | 2019-01-17 17:00:14 +0000 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2019-01-19 15:45:41 +0000 |
| commit | 3c4c18341aafbdd0c24665a56d0af32b1e4dc981 (patch) | |
| tree | 11b8f3e43720705042695cb165682dc2ce4b5f13 /src/intel/vulkan/genX_cmd_buffer.c | |
| parent | 6ca652faf368427e3e6d57ef5456f78203b8207e (diff) | |
anv: narrow flushing of the render target to buffer writes
In commit 9a7b3199037ac4 ("anv/query: flush render target before
copying results") we tracked all the render target writes to apply a
flushes in the vkCopyQueryResults(). But we can narrow this down to
only when we write a buffer (which is the only input of
vkCopyQueryResults).
v2: Drop newer render target write flags introduce by 1952fd8d2ce905
("anv: Implement VK_EXT_conditional_rendering for gen 7.5+")
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]> (v1)
Diffstat (limited to 'src/intel/vulkan/genX_cmd_buffer.c')
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index e69c169b9ba..2d94d85d141 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1811,7 +1811,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * saying that render target writes are ongoing. */ if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT) - bits &= ~(ANV_PIPE_RENDER_TARGET_WRITES); + bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES); bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT); } @@ -2828,8 +2828,6 @@ void genX(CmdDraw)( prim.StartInstanceLocation = firstInstance; prim.BaseVertexLocation = 0; } - - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES; } void genX(CmdDrawIndexed)( @@ -2873,8 +2871,6 @@ void genX(CmdDrawIndexed)( prim.StartInstanceLocation = firstInstance; prim.BaseVertexLocation = vertexOffset; } - - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES; } /* Auto-Draw / Indirect Registers */ @@ -3012,8 +3008,6 @@ void genX(CmdDrawIndirect)( offset += stride; } - - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES; } void genX(CmdDrawIndexedIndirect)( @@ -3057,8 +3051,6 @@ void genX(CmdDrawIndexedIndirect)( offset += stride; } - - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES; } #define TMP_DRAW_COUNT_REG MI_ALU_REG14 @@ -3218,8 +3210,6 @@ void genX(CmdDrawIndirectCountKHR)( offset += stride; } - - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES; } void genX(CmdDrawIndexedIndirectCountKHR)( @@ -3280,8 +3270,6 @@ void genX(CmdDrawIndexedIndirectCountKHR)( offset += stride; } - - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES; } static VkResult |