diff options
| author | Rafael Antognolli <[email protected]> | 2020-02-21 12:03:05 -0800 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-03-03 16:25:54 +0000 |
| commit | cd40110420b48b3005c9d1d4ea30e2cbcc9a3d40 (patch) | |
| tree | 068eec7958a10d06cd47f67f7f00dc09ac5d7e6b /src/intel/genxml | |
| parent | 9fea90ad5170dd64376d22a14ac88c392813c96c (diff) | |
intel/isl: Implement D16_UNORM workarounds.
GEN:BUG:14010455700 (lineage 1808121037):
"To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"
Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501.
GEN:BUG:1806527549:
"Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM."
This one could fix a GPU hang in some workloads.
v2: Implement WA in isl and add another similar WA (Jason).
v3: Add flushes before changing chicken registers (Jason)
v4: Depth flush and stall + end of pipe sync when changing registers
(Jason).
Reviewed-by: Jason Ekstrand <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
Diffstat (limited to 'src/intel/genxml')
| -rw-r--r-- | src/intel/genxml/gen12.xml | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 6ed9ccc369e..127bc549a8b 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -7032,6 +7032,16 @@ <field name="CL Primitives Count Report" start="0" end="63" type="uint"/> </register> + <register name="COMMON_SLICE_CHICKEN1" length="1" num="0x7010"> + <field name="HIZ Plane Optimization disable bit" start="9" end="9" type="bool"/> + <field name="HIZ Plane Optimization disable bit Mask" start="25" end="25" type="bool"/> + </register> + + <register name="HIZ_CHICKEN" length="1" num="0x7018"> + <field name="HZ Depth Test LE/GE Optimization Disable" start="13" end="13" type="bool"/> + <field name="HZ Depth Test LE/GE Optimization Disable Mask" start="29" end="29" type="bool"/> + </register> + <register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304"> <field name="PS Thread Panic Dispatch" start="6" end="7" type="uint"/> <field name="PS Thread Panic Dispatch Mask" start="22" end="23" type="uint"/> |