From cd40110420b48b3005c9d1d4ea30e2cbcc9a3d40 Mon Sep 17 00:00:00 2001 From: Rafael Antognolli Date: Fri, 21 Feb 2020 12:03:05 -0800 Subject: intel/isl: Implement D16_UNORM workarounds. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GEN:BUG:14010455700 (lineage 1808121037): "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501. GEN:BUG:1806527549: "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM." This one could fix a GPU hang in some workloads. v2: Implement WA in isl and add another similar WA (Jason). v3: Add flushes before changing chicken registers (Jason) v4: Depth flush and stall + end of pipe sync when changing registers (Jason). Reviewed-by: Jason Ekstrand Tested-by: Marge Bot Part-of: --- src/intel/genxml/gen12.xml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/intel/genxml') diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index 6ed9ccc369e..127bc549a8b 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -7032,6 +7032,16 @@ + + + + + + + + + + -- cgit v1.2.3