diff options
| author | Anuj Phogat <[email protected]> | 2018-10-12 14:12:50 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-11-01 12:00:23 -0700 |
| commit | 13c955182f1d87eea513a15b9d57dd0aec8d1038 (patch) | |
| tree | 5e377d2266600c5a5b9202e604bed2b1ee3e7566 /src/intel/genxml/gen11.xml | |
| parent | b3d6937fb0d31baa77a3caf519458a86de8d202d (diff) | |
anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG
The default setting of this bit is not the desirable behavior.
WA_1406697149
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/intel/genxml/gen11.xml')
| -rw-r--r-- | src/intel/genxml/gen11.xml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index c69d7dc89c2..454ef8f4103 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3546,6 +3546,7 @@ <register name="L3CNTLREG" length="1" num="0x7034"> <field name="SLM Enable" start="0" end="0" type="uint"/> <field name="URB Allocation" start="1" end="7" type="uint"/> + <field name="Error Detection Behavior Control" start="9" end="9" type="bool"/> <field name="RO Allocation" start="11" end="17" type="uint"/> <field name="DC Allocation" start="18" end="24" type="uint"/> <field name="All Allocation" start="25" end="31" type="uint"/> |