diff options
| author | Matt Turner <[email protected]> | 2017-06-14 16:20:41 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2018-02-28 11:15:47 -0800 |
| commit | 89fe5190a256ee0939061c4c264e9156256d16e8 (patch) | |
| tree | 01a231a3cd2109f134c285a6caa715eec95a6e2a /src/intel/compiler/brw_vec4_visitor.cpp | |
| parent | 2134ea380033d5d1f3c5760b8bdb1da7aadd9842 (diff) | |
intel/compiler: Lower flrp32 on Gen11+
The LRP instruction is no more.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_vec4_visitor.cpp')
| -rw-r--r-- | src/intel/compiler/brw_vec4_visitor.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_vec4_visitor.cpp b/src/intel/compiler/brw_vec4_visitor.cpp index 53f6a5ed546..e683a8c51db 100644 --- a/src/intel/compiler/brw_vec4_visitor.cpp +++ b/src/intel/compiler/brw_vec4_visitor.cpp @@ -735,7 +735,7 @@ vec4_instruction * vec4_visitor::emit_lrp(const dst_reg &dst, const src_reg &x, const src_reg &y, const src_reg &a) { - if (devinfo->gen >= 6) { + if (devinfo->gen >= 6 && devinfo->gen <= 10) { /* Note that the instruction's argument order is reversed from GLSL * and the IR. */ |