diff options
| author | Matt Turner <[email protected]> | 2020-02-27 19:49:35 -0800 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-03-09 04:44:12 +0000 |
| commit | edae75037fe52a88d5f1d6c44484d714fac944d6 (patch) | |
| tree | 9b4cdd685f75a2e231a064d5613d80dde9bc6a8a /src/intel/compiler/brw_schedule_instructions.cpp | |
| parent | 75a33e268ea4eed0391b1f77948337b747834545 (diff) | |
intel/compiler: Mark visitor parameters to scheduler const
Reviewed-by: Ian Romanick <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4093>
Diffstat (limited to 'src/intel/compiler/brw_schedule_instructions.cpp')
| -rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index de4fdd0239f..a4a6f172c9c 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -533,11 +533,11 @@ schedule_node::set_latency_gen7(bool is_haswell) class instruction_scheduler { public: - instruction_scheduler(backend_shader *s, int grf_count, + instruction_scheduler(const backend_shader *s, int grf_count, unsigned hw_reg_count, int block_count, - instruction_scheduler_mode mode) + instruction_scheduler_mode mode): + bs(s) { - this->bs = s; this->mem_ctx = ralloc_context(NULL); this->grf_count = grf_count; this->hw_reg_count = hw_reg_count; @@ -617,7 +617,7 @@ public: int reg_pressure; int block_idx; exec_list instructions; - backend_shader *bs; + const backend_shader *bs; instruction_scheduler_mode mode; @@ -667,14 +667,14 @@ public: class fs_instruction_scheduler : public instruction_scheduler { public: - fs_instruction_scheduler(fs_visitor *v, int grf_count, int hw_reg_count, + fs_instruction_scheduler(const fs_visitor *v, int grf_count, int hw_reg_count, int block_count, instruction_scheduler_mode mode); void calculate_deps(); bool is_compressed(fs_inst *inst); schedule_node *choose_instruction_to_schedule(); int issue_time(backend_instruction *inst); - fs_visitor *v; + const fs_visitor *v; void count_reads_remaining(backend_instruction *inst); void setup_liveness(cfg_t *cfg); @@ -682,7 +682,7 @@ public: int get_register_pressure_benefit(backend_instruction *inst); }; -fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor *v, +fs_instruction_scheduler::fs_instruction_scheduler(const fs_visitor *v, int grf_count, int hw_reg_count, int block_count, instruction_scheduler_mode mode) @@ -848,11 +848,11 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be) class vec4_instruction_scheduler : public instruction_scheduler { public: - vec4_instruction_scheduler(vec4_visitor *v, int grf_count); + vec4_instruction_scheduler(const vec4_visitor *v, int grf_count); void calculate_deps(); schedule_node *choose_instruction_to_schedule(); int issue_time(backend_instruction *inst); - vec4_visitor *v; + const vec4_visitor *v; void count_reads_remaining(backend_instruction *inst); void setup_liveness(cfg_t *cfg); @@ -860,7 +860,7 @@ public: int get_register_pressure_benefit(backend_instruction *inst); }; -vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor *v, +vec4_instruction_scheduler::vec4_instruction_scheduler(const vec4_visitor *v, int grf_count) : instruction_scheduler(v, grf_count, 0, 0, SCHEDULE_POST), v(v) |