diff options
| author | Francisco Jerez <[email protected]> | 2017-12-06 11:42:54 -0800 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2017-12-07 15:56:49 -0800 |
| commit | acf98ff933d338c521d7c6a57c17a010149eb344 (patch) | |
| tree | 07af8a02ab269b0679ee9f7320acc4cbe7ad7f81 /src/intel/compiler/brw_schedule_instructions.cpp | |
| parent | af2c320190f3c73180f1610c8df955a7fa2a4d09 (diff) | |
intel/fs: Teach instruction scheduler about GRF bank conflict cycles.
This should allow the post-RA scheduler to do a slightly better job at
hiding latency in presence of instructions incurring bank conflicts.
The main purpuse of this patch is not to improve performance though,
but to get conflict cycles to show up in shader-db statistics in order
to make sure that regressions in the bank conflict mitigation pass
don't go unnoticed.
Acked-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_schedule_instructions.cpp')
| -rw-r--r-- | src/intel/compiler/brw_schedule_instructions.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index a1e825c661c..692f7125323 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -1543,10 +1543,11 @@ vec4_instruction_scheduler::choose_instruction_to_schedule() int fs_instruction_scheduler::issue_time(backend_instruction *inst) { + const unsigned overhead = v->bank_conflict_cycles((fs_inst *)inst); if (is_compressed((fs_inst *)inst)) - return 4; + return 4 + overhead; else - return 2; + return 2 + overhead; } int |