From acf98ff933d338c521d7c6a57c17a010149eb344 Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Wed, 6 Dec 2017 11:42:54 -0800 Subject: intel/fs: Teach instruction scheduler about GRF bank conflict cycles. This should allow the post-RA scheduler to do a slightly better job at hiding latency in presence of instructions incurring bank conflicts. The main purpuse of this patch is not to improve performance though, but to get conflict cycles to show up in shader-db statistics in order to make sure that regressions in the bank conflict mitigation pass don't go unnoticed. Acked-by: Matt Turner --- src/intel/compiler/brw_schedule_instructions.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/intel/compiler/brw_schedule_instructions.cpp') diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index a1e825c661c..692f7125323 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -1543,10 +1543,11 @@ vec4_instruction_scheduler::choose_instruction_to_schedule() int fs_instruction_scheduler::issue_time(backend_instruction *inst) { + const unsigned overhead = v->bank_conflict_cycles((fs_inst *)inst); if (is_compressed((fs_inst *)inst)) - return 4; + return 4 + overhead; else - return 2; + return 2 + overhead; } int -- cgit v1.2.3