diff options
author | Ian Romanick <[email protected]> | 2018-05-22 18:56:41 -0700 |
---|---|---|
committer | Ian Romanick <[email protected]> | 2019-03-28 15:35:53 -0700 |
commit | 7832fb78898cf98c02e132609187fce84b5000fd (patch) | |
tree | 19c089573c68071c5ceb10431b8d676fdcaddc40 /src/intel/compiler/brw_nir.c | |
parent | 2cf59861a8128a91bfdd6fe62bf69cb4593373e3 (diff) |
intel/compiler: Use partial redundancy elimination for compares
Almost all of the hurt shaders are repeated instances of the same shader
in synmark's compilation speed tests.
shader-db results:
All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15256840 -> 15256389 (<.01%)
instructions in affected programs: 54137 -> 53686 (-0.83%)
helped: 288
HURT: 0
helped stats (abs) min: 1 max: 15 x̄: 1.57 x̃: 1
helped stats (rel) min: 0.06% max: 26.67% x̄: 1.99% x̃: 0.74%
95% mean confidence interval for instructions value: -1.76 -1.38
95% mean confidence interval for instructions %-change: -2.47% -1.50%
Instructions are helped.
total cycles in shared programs: 372286583 -> 372283851 (<.01%)
cycles in affected programs: 833829 -> 831097 (-0.33%)
helped: 265
HURT: 16
helped stats (abs) min: 2 max: 74 x̄: 11.81 x̃: 4
helped stats (rel) min: 0.04% max: 9.07% x̄: 0.99% x̃: 0.35%
HURT stats (abs) min: 2 max: 130 x̄: 24.88 x̃: 8
HURT stats (rel) min: <.01% max: 12.31% x̄: 1.44% x̃: 0.27%
95% mean confidence interval for cycles value: -12.30 -7.15
95% mean confidence interval for cycles %-change: -1.06% -0.64%
Cycles are helped.
Iron Lake and GM45 had similar results. (GM45 shown)
total instructions in shared programs: 5038653 -> 5038495 (<.01%)
instructions in affected programs: 13939 -> 13781 (-1.13%)
helped: 50
HURT: 1
helped stats (abs) min: 1 max: 15 x̄: 3.18 x̃: 4
helped stats (rel) min: 0.33% max: 13.33% x̄: 2.24% x̃: 1.09%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.83% max: 0.83% x̄: 0.83% x̃: 0.83%
95% mean confidence interval for instructions value: -3.73 -2.47
95% mean confidence interval for instructions %-change: -3.16% -1.21%
Instructions are helped.
total cycles in shared programs: 128118922 -> 128118228 (<.01%)
cycles in affected programs: 134906 -> 134212 (-0.51%)
helped: 50
HURT: 0
helped stats (abs) min: 2 max: 60 x̄: 13.88 x̃: 18
helped stats (rel) min: 0.06% max: 3.19% x̄: 0.74% x̃: 0.70%
95% mean confidence interval for cycles value: -16.54 -11.22
95% mean confidence interval for cycles %-change: -0.95% -0.53%
Cycles are helped.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_nir.c')
-rw-r--r-- | src/intel/compiler/brw_nir.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 370b66dc57d..238db902b47 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -853,6 +853,26 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, OPT(brw_nir_opt_peephole_ffma); } + if (OPT(nir_opt_comparison_pre)) { + OPT(nir_copy_prop); + OPT(nir_opt_dce); + OPT(nir_opt_cse); + + /* Do the select peepehole again. nir_opt_comparison_pre (combined with + * the other optimization passes) will have removed at least one + * instruction from one of the branches of the if-statement, so now it + * might be under the threshold of conversion to bcsel. + * + * See brw_nir_optimize for the explanation of is_vec4_tessellation. + */ + const bool is_vec4_tessellation = !is_scalar && + (nir->info.stage == MESA_SHADER_TESS_CTRL || + nir->info.stage == MESA_SHADER_TESS_EVAL); + OPT(nir_opt_peephole_select, 0, is_vec4_tessellation, false); + OPT(nir_opt_peephole_select, 1, is_vec4_tessellation, + compiler->devinfo->gen >= 6); + } + OPT(nir_opt_algebraic_late); OPT(nir_lower_to_source_mods, nir_lower_all_source_mods); |