diff options
| author | Matt Turner <[email protected]> | 2017-06-14 16:04:07 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2017-10-20 15:00:17 -0700 |
| commit | f11fa5ac6c5f955097c79e6bf27cd1a437c90ca5 (patch) | |
| tree | 1547cbd52265a8ecd4ec0ab75c73d9e61d301411 /src/intel/compiler/brw_eu_defines.h | |
| parent | 6c7fc9b73a2919dbc246a888002210d7e4b9818b (diff) | |
i965: Add align1 ternary instruction disassembler support
Reviewed-by: Scott D Phillips <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_defines.h')
| -rw-r--r-- | src/intel/compiler/brw_eu_defines.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 3af55e830cf..291dd361a29 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -837,17 +837,6 @@ enum PACKED gen10_align1_3src_reg_file { BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */ }; -/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so - * the types were implied. IVB adds BFE and BFI2 that operate on doublewords - * and unsigned doublewords, so a new field is also available in the da3src - * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select - * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*. - */ -#define BRW_3SRC_TYPE_F 0 -#define BRW_3SRC_TYPE_D 1 -#define BRW_3SRC_TYPE_UD 2 -#define BRW_3SRC_TYPE_DF 3 - /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction * word is "Execution Datatype" which controls whether the instruction operates * on float or integer types. The register arguments have fields that offer |