diff options
| author | Matt Turner <[email protected]> | 2018-02-12 16:26:20 -0800 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2019-10-30 11:11:50 -0700 |
| commit | d0eff8a539fbd14e29a4ff2618114c5b9e01e9fb (patch) | |
| tree | 02d08738dc971e1752d2e0116b4d165453da7227 /src/intel/compiler/brw_eu_compact.c | |
| parent | ded9fb2b18b114d311a5425916b64a12fb7ff36b (diff) | |
intel/compiler: Restructure instruction compaction in preparation for Gen12
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Diffstat (limited to 'src/intel/compiler/brw_eu_compact.c')
| -rw-r--r-- | src/intel/compiler/brw_eu_compact.c | 48 |
1 files changed, 28 insertions, 20 deletions
diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index 6198ad63ba5..afe87a82a6c 100644 --- a/src/intel/compiler/brw_eu_compact.c +++ b/src/intel/compiler/brw_eu_compact.c @@ -708,20 +708,24 @@ static bool set_control_index(const struct gen_device_info *devinfo, brw_compact_inst *dst, const brw_inst *src) { - uint32_t uncompacted = devinfo->gen >= 8 /* 17b/G45; 19b/IVB+ */ - ? (brw_inst_bits(src, 33, 31) << 16) | /* 3b */ - (brw_inst_bits(src, 23, 12) << 4) | /* 12b */ - (brw_inst_bits(src, 10, 9) << 2) | /* 2b */ - (brw_inst_bits(src, 34, 34) << 1) | /* 1b */ - (brw_inst_bits(src, 8, 8)) /* 1b */ - : (brw_inst_bits(src, 31, 31) << 16) | /* 1b */ - (brw_inst_bits(src, 23, 8)); /* 16b */ - - /* On gen7, the flag register and subregister numbers are integrated into - * the control index. - */ - if (devinfo->gen == 7) - uncompacted |= brw_inst_bits(src, 90, 89) << 17; /* 2b */ + uint32_t uncompacted; /* 17b/G45; 19b/IVB+ */ + + if (devinfo->gen >= 8) { + uncompacted = (brw_inst_bits(src, 33, 31) << 16) | /* 3b */ + (brw_inst_bits(src, 23, 12) << 4) | /* 12b */ + (brw_inst_bits(src, 10, 9) << 2) | /* 2b */ + (brw_inst_bits(src, 34, 34) << 1) | /* 1b */ + (brw_inst_bits(src, 8, 8)); /* 1b */ + } else { + uncompacted = (brw_inst_bits(src, 31, 31) << 16) | /* 1b */ + (brw_inst_bits(src, 23, 8)); /* 16b */ + + /* On gen7, the flag register and subregister numbers are integrated into + * the control index. + */ + if (devinfo->gen == 7) + uncompacted |= brw_inst_bits(src, 90, 89) << 17; /* 2b */ + } for (int i = 0; i < 32; i++) { if (control_index_table[i] == uncompacted) { @@ -737,12 +741,16 @@ static bool set_datatype_index(const struct gen_device_info *devinfo, brw_compact_inst *dst, const brw_inst *src) { - uint32_t uncompacted = devinfo->gen >= 8 /* 18b/G45+; 21b/BDW+ */ - ? (brw_inst_bits(src, 63, 61) << 18) | /* 3b */ - (brw_inst_bits(src, 94, 89) << 12) | /* 6b */ - (brw_inst_bits(src, 46, 35)) /* 12b */ - : (brw_inst_bits(src, 63, 61) << 15) | /* 3b */ - (brw_inst_bits(src, 46, 32)); /* 15b */ + uint32_t uncompacted; /* 18b/G45+; 21b/BDW+ */ + + if (devinfo->gen >= 8) { + uncompacted = (brw_inst_bits(src, 63, 61) << 18) | /* 3b */ + (brw_inst_bits(src, 94, 89) << 12) | /* 6b */ + (brw_inst_bits(src, 46, 35)); /* 12b */ + } else { + uncompacted = (brw_inst_bits(src, 63, 61) << 15) | /* 3b */ + (brw_inst_bits(src, 46, 32)); /* 15b */ + } for (int i = 0; i < 32; i++) { if (datatype_table[i] == uncompacted) { |