diff options
| author | Lionel Landwerlin <[email protected]> | 2020-01-15 15:13:43 +0200 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2020-01-16 11:48:11 +0200 |
| commit | e6e5cbac04c950ecc37cb9de45c24d15a54cafc7 (patch) | |
| tree | fe8d5dcec0486890ae965eb19c0b9f5ab2e69b94 /src/gallium | |
| parent | 31f0af5568478fb696307438f270f7fc31e1db89 (diff) | |
iris: handle new PIPE_CONTROL field
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/iris/iris_context.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 6 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 0d8e62ea085..50300f9c2a6 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -297,6 +297,7 @@ enum pipe_control_flags PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23), PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24), PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25), + PIPE_CONTROL_FLUSH_HDC = (1 << 26), }; #define PIPE_CONTROL_CACHE_FLUSH_BITS \ diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 67d9f758ef7..e872b14cf18 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -7152,7 +7152,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, if (INTEL_DEBUG & DEBUG_PIPE_CONTROL) { fprintf(stderr, - " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n", + " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n", (flags & PIPE_CONTROL_FLUSH_ENABLE) ? "PipeCon " : "", (flags & PIPE_CONTROL_CS_STALL) ? "CS " : "", (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD) ? "Scoreboard " : "", @@ -7175,6 +7175,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, (flags & PIPE_CONTROL_WRITE_IMMEDIATE) ? "WriteImm " : "", (flags & PIPE_CONTROL_WRITE_DEPTH_COUNT) ? "WriteZCount " : "", (flags & PIPE_CONTROL_WRITE_TIMESTAMP) ? "WriteTimestamp " : "", + (flags & PIPE_CONTROL_FLUSH_HDC) ? "HDC " : "", imm, reason); } @@ -7182,6 +7183,9 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, #if GEN_GEN >= 12 pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH; #endif +#if GEN_GEN >= 11 + pc.HDCPipelineFlushEnable = flags & PIPE_CONTROL_FLUSH_HDC; +#endif pc.LRIPostSyncOperation = NoLRIOperation; pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE; pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH; |