diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-02 12:10:43 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-27 08:04:05 +0200 |
| commit | d62d2840c42d0eb3433c6c0c8bfe8d506c0475b9 (patch) | |
| tree | 15dc1af10891dce96f59d2881de6c3e1999a8cdd /src/gallium | |
| parent | af65f9431e0fea5df0957987efeb0b87cee6cadc (diff) | |
ac: add has_clear_state to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_gfx_cs.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 2 |
4 files changed, 2 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index b30839d25b5..f34286ecaec 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -372,7 +372,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx) ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS; /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */ - bool has_clear_state = ctx->screen->has_clear_state; + bool has_clear_state = ctx->screen->info.has_clear_state; if (has_clear_state) { ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs); diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 475c15c54ba..21e785dd44f 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1109,12 +1109,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers); } - /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs - * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. - * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. */ - sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 && - sscreen->info.is_amdgpu; - sscreen->has_distributed_tess = sscreen->info.chip_class >= GFX8 && sscreen->info.max_se >= 2; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 7fd13cfa9e7..4630fff7357 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -491,7 +491,6 @@ struct si_screen { unsigned eqaa_force_coverage_samples; unsigned eqaa_force_z_samples; unsigned eqaa_force_color_samples; - bool has_clear_state; bool has_distributed_tess; bool has_draw_indirect_multi; bool has_out_of_order_rast; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 05844abe360..d5cdc660350 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5390,7 +5390,7 @@ static void si_init_config(struct si_context *sctx) { struct si_screen *sscreen = sctx->screen; uint64_t border_color_va = sctx->border_color_buffer->gpu_address; - bool has_clear_state = sscreen->has_clear_state; + bool has_clear_state = sscreen->info.has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); if (!pm4) |