diff options
| author | Marek Olšák <[email protected]> | 2020-05-02 09:19:18 -0400 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-05-07 20:13:41 +0000 |
| commit | cf61f635ff6a38aad344ebe30551eaaac6fec038 (patch) | |
| tree | 174214d14220666d4bab00ae1eb28c613cd95b21 /src/gallium | |
| parent | 127aaf0b9ac1eb46633df35c899b5d1a175a7220 (diff) | |
amd: assume CMASK is always rb/pipe_aligned, remove ac_surface.u.gfx9.cmask
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 15 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_texture.c | 5 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 2f6c437a58b..5fef04b3cb2 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3049,7 +3049,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_attrib3 = cb->cb_color_attrib3 | S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) | S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) | - S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) | + S_028EE0_CMASK_PIPE_ALIGNED(1) | S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned); radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14); @@ -3077,12 +3077,13 @@ static void si_emit_framebuffer_state(struct si_context *sctx) radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2); radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3); } else if (sctx->chip_class == GFX9) { - struct gfx9_surf_meta_flags meta; + struct gfx9_surf_meta_flags meta = { + .rb_aligned = 1, + .pipe_aligned = 1, + }; if (tex->surface.dcc_offset) meta = tex->surface.u.gfx9.dcc; - else - meta = tex->surface.u.gfx9.cmask; /* Set mutable surface parameters. */ cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; @@ -3878,7 +3879,7 @@ static void gfx10_make_texture_descriptor( S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0)); fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer); fmask_state[5] = 0; - fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned); + fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1); fmask_state[7] = 0; } } @@ -4201,8 +4202,8 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode); fmask_state[4] |= S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch); - fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) | - S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned); + fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) | + S_008F24_META_RB_ALIGNED(1); } else { fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index); fmask_state[4] |= S_008F20_DEPTH(depth - 1) | diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 1c2c170c97e..2ec19e5f28d 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -1065,10 +1065,9 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex, if (tex->cmask_buffer) { u_log_printf(log, " CMask: offset=%" PRIu64 ", size=%u, " - "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n", + "alignment=%u\n", tex->surface.cmask_offset, tex->surface.cmask_size, - tex->surface.cmask_alignment, tex->surface.u.gfx9.cmask.rb_aligned, - tex->surface.u.gfx9.cmask.pipe_aligned); + tex->surface.cmask_alignment); } if (tex->surface.htile_offset) { |