diff options
| author | Rafael Antognolli <[email protected]> | 2020-02-21 12:03:05 -0800 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-03-03 16:25:54 +0000 |
| commit | cd40110420b48b3005c9d1d4ea30e2cbcc9a3d40 (patch) | |
| tree | 068eec7958a10d06cd47f67f7f00dc09ac5d7e6b /src/gallium | |
| parent | 9fea90ad5170dd64376d22a14ac88c392813c96c (diff) | |
intel/isl: Implement D16_UNORM workarounds.
GEN:BUG:14010455700 (lineage 1808121037):
"To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer
Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA"
Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501.
GEN:BUG:1806527549:
"Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM."
This one could fix a GPU hang in some workloads.
v2: Implement WA in isl and add another similar WA (Jason).
v3: Add flushes before changing chicken registers (Jason)
v4: Depth flush and stall + end of pipe sync when changing registers
(Jason).
Reviewed-by: Jason Ekstrand <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 3a2d7140c1e..5574b073a79 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1056,7 +1056,8 @@ struct iris_depth_buffer_state { uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) + GENX(3DSTATE_STENCIL_BUFFER_length) + GENX(3DSTATE_HIER_DEPTH_BUFFER_length) + - GENX(3DSTATE_CLEAR_PARAMS_length)]; + GENX(3DSTATE_CLEAR_PARAMS_length) + + GENX(MI_LOAD_REGISTER_IMM_length) * 2]; }; /** @@ -5900,7 +5901,22 @@ iris_upload_dirty_render_state(struct iris_context *ice, * first. */ uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4; - uint32_t cso_z_size = sizeof(cso_z->packets) - clear_length; + uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;; + +#if GEN_GEN == 12 + /* GEN:BUG:14010455700 + * + * ISL will change some CHICKEN registers depending on the depth surface + * format, along with emitting the depth and stencil packets. In that + * case, we want to do a depth flush and stall, so the pipeline is not + * using these settings while we change the registers. + */ + iris_emit_end_of_pipe_sync(batch, + "Workaround: Stop pipeline for 14010455700", + PIPE_CONTROL_DEPTH_STALL | + PIPE_CONTROL_DEPTH_CACHE_FLUSH); +#endif + iris_batch_emit(batch, cso_z->packets, cso_z_size); if (GEN_GEN >= 12) { /* GEN:BUG:1408224581 |