diff options
| author | Marek Olšák <[email protected]> | 2017-06-16 14:25:34 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-06-22 13:15:27 +0200 |
| commit | c9040dc9e75c81024f88f3f1bab821ad2bc73db3 (patch) | |
| tree | 8fbd7c76f995963b81a03240f9148a9ec7690556 /src/gallium | |
| parent | 5352174d49f8a720243429934aa634556eece159 (diff) | |
radeonsi: don't emit partial flushes at the end of IBs (v2)
The kernel sort of does the same thing with fences.
v2: do emit partial flushes on SI
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index 345825af002..76b295f9ecd 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -129,13 +129,17 @@ void si_context_gfx_flush(void *context, unsigned flags, r600_preflush_suspend_features(&ctx->b); - ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | - SI_CONTEXT_PS_PARTIAL_FLUSH; - /* DRM 3.1.0 doesn't flush TC for VI correctly. */ - if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) - ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 | + if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1) { + ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | + SI_CONTEXT_CS_PARTIAL_FLUSH | + SI_CONTEXT_INV_GLOBAL_L2 | SI_CONTEXT_INV_VMEM_L1; + } else if (ctx->b.chip_class == SI) { + /* The kernel doesn't wait for idle before doing SURFACE_SYNC. */ + ctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | + SI_CONTEXT_CS_PARTIAL_FLUSH; + } si_emit_cache_flush(ctx); |