diff options
| author | Marek Olšák <[email protected]> | 2015-08-30 17:39:03 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-09-01 21:51:15 +0200 |
| commit | ba79ff7fa8c202ea9c55c0764118be481beb8a83 (patch) | |
| tree | a32fd41b5fc73c1df040174a6c54ca825fc936f8 /src/gallium | |
| parent | 0f4688fbe7237c4bc5b9849e90452a9731cd3748 (diff) | |
winsys/amdgpu: remove IB padding for SI
SI is unsupported by amdgpu
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 3e9fc4023b3..84fc40b923d 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c @@ -601,25 +601,13 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs, switch (cs->base.ring_type) { case RING_DMA: /* pad DMA ring to 8 DWs */ - if (ws->info.chip_class <= SI) { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0xf0000000); /* NOP packet */ - } else { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0x00000000); /* NOP packet */ - } + while (rcs->cdw & 7) + OUT_CS(&cs->base, 0x00000000); /* NOP packet */ break; case RING_GFX: - /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements - * r6xx, requires at least 4 dw alignment to avoid a hw bug. - */ - if (ws->info.chip_class <= SI) { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0x80000000); /* type2 nop packet */ - } else { - while (rcs->cdw & 7) - OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */ - } + /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */ + while (rcs->cdw & 7) + OUT_CS(&cs->base, 0xffff1000); /* type3 nop packet */ break; case RING_UVD: while (rcs->cdw & 15) |