r600g: don't require dword alignment with CP DMA for buffer transfers

which is a leftover from the days when we used streamout to copy buffers

Tested-by: Andreas Boll <[email protected]>

5 files changed, 9 insertions, 11 deletions

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index c737aa25c43..8fc83aaad25 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -508,8 +508,7 @@ void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsig
 {
 	struct r600_context *rctx = (struct r600_context*)ctx;
 
-	/* CP DMA doesn't work on R600 (flushing seems to be unreliable). */
-	if (rctx->screen->info.drm_minor >= 27 && rctx->chip_class >= R700) {
+	if (rctx->screen->has_cp_dma) {
 		r600_cp_dma_copy_buffer(rctx, dst, dstx, src, src_box->x, src_box->width);
 	}
 	else if (rctx->screen->has_streamout &&
diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c
index 7574cd6c889..4dbe363da82 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -150,9 +150,10 @@ static void *r600_buffer_transfer_map(struct pipe_context *ctx,
 	}
 	else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 		 !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
-		 rctx->screen->has_streamout &&
-		 /* The buffer range must be aligned to 4. */
-		 box->x % 4 == 0 && box->width % 4 == 0) {
+		 (rctx->screen->has_cp_dma ||
+		  (rctx->screen->has_streamout &&
+		   /* The buffer range must be aligned to 4 with streamout. */
+		   box->x % 4 == 0 && box->width % 4 == 0))) {
 		assert(usage & PIPE_TRANSFER_WRITE);
 
 		/* Check if mapping this buffer would cause waiting for the GPU. */
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index c2f3aab7813..677c6fca4f4 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1087,12 +1087,7 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
 	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 
 	assert(size);
-	assert(rctx->chip_class != R600);
-
-	/* CP DMA doesn't work on R600 (flushing seems to be unreliable). */
-	if (rctx->chip_class == R600) {
-		return;
-	}
+	assert(rctx->screen->has_cp_dma);
 
 	dst_offset += r600_resource_va(&rctx->screen->screen, dst);
 	src_offset += r600_resource_va(&rctx->screen->screen, src);
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index a0504d14291..e81856c5f33 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -1123,6 +1123,8 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
 		break;
 	}
 
+	rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 && rscreen->chip_class >= R700;
+
 	if (r600_init_tiling(rscreen)) {
 		FREE(rscreen);
 		return NULL;
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index f9519d796c6..cb520833c1c 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -232,6 +232,7 @@ struct r600_screen {
 	struct radeon_info		info;
 	bool				has_streamout;
 	bool				has_msaa;
+	bool				has_cp_dma;
 	enum r600_msaa_texture_mode	msaa_texture_support;
 	bool				use_hyperz;
 	struct r600_tiling_info		tiling_info;