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authorMarek Olšák <[email protected]>2017-07-29 01:14:09 +0200
committerMarek Olšák <[email protected]>2017-08-04 02:10:04 +0200
commit4a758a17da7dd7366b98cee9b6312bf350102ad1 (patch)
treeaf2a5e811e5e36f3605193cc0ef058c67f92fbfa /src/gallium
parentc60c5accd1b20514dbbbbab7ac40004ad7122b44 (diff)
winsys/amdgpu: enable computation of tile swizzle
Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c12
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h2
2 files changed, 13 insertions, 1 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index d438b6d662b..99e4d778df2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -92,7 +92,17 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
config.info.levels = tex->last_level + 1;
config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
- config.info.surf_index = NULL;
+
+ /* Use different surface counters for color and FMASK, so that MSAA MRTs
+ * always use consecutive surface indices when FMASK is allocated between
+ * them.
+ */
+ if (flags & RADEON_SURF_FMASK)
+ config.info.surf_index = &ws->surf_index_fmask;
+ else if (!(flags & RADEON_SURF_Z_OR_SBUFFER))
+ config.info.surf_index = &ws->surf_index_color;
+ else
+ config.info.surf_index = NULL;
return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
}
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index 7cd2f204842..7aca612f452 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -57,6 +57,8 @@ struct amdgpu_winsys {
int num_cs; /* The number of command streams created. */
unsigned num_total_rejected_cs;
+ uint32_t surf_index_color;
+ uint32_t surf_index_fmask;
uint32_t next_bo_unique_id;
uint64_t allocated_vram;
uint64_t allocated_gtt;