diff options
author | Marek Olšák <[email protected]> | 2017-01-24 03:41:05 +0100 |
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committer | Marek Olšák <[email protected]> | 2017-01-30 13:27:14 +0100 |
commit | 4a4ff66dbebe836492a6b6321742c21ca9bcd70a (patch) | |
tree | 1e3a1391b490ee9cb7e46239a3e3e4534bd55b5e /src/gallium | |
parent | 879c73fac8a8bfc8495e2e9876c4aa9b78006d4b (diff) |
radeonsi: also prefetch compute shaders
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_compute.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index fe29fb154d5..d05c488f38c 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -372,6 +372,18 @@ static bool si_switch_compute_shader(struct si_context *sctx, RADEON_PRIO_SCRATCH_BUFFER); } + /* Prefetch the compute shader to TC L2. + * + * We should also prefetch graphics shaders if a compute dispatch was + * the last command, and the compute shader if a draw call was the last + * command. However, that would add more complexity and we're likely + * to get a shader state change in that case anyway. + */ + if (sctx->b.chip_class >= CIK) { + cik_prefetch_TC_L2_async(sctx, &program->shader.bo->b.b, + 0, program->shader.bo->b.b.width0); + } + shader_va = shader->bo->gpu_address + offset; if (program->use_code_object_v2) { /* Shader code is placed after the amd_kernel_code_t |