ac: rename SI-CIK-VI to GFX6-GFX7-GFX8

Acked-by: Dave Airlie <[email protected]>

We already use GFX9 and I don't want us to have confusing naming
in the driver. GFXn naming is better from the driver perspective,
because it's the real version of the gfx portion of the hw. Also,
CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI.

It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have
nothing to do with GFXn and they have their own version numbers.

3 files changed, 19 insertions, 19 deletions

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 490c246d6e0..43185366803 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -552,7 +552,7 @@ static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs,
     switch (cs->ring_type) {
     case RING_DMA:
         /* pad DMA ring to 8 DWs */
-        if (cs->ws->info.chip_class <= SI) {
+        if (cs->ws->info.chip_class <= GFX6) {
             while (rcs->current.cdw & 7)
                 radeon_emit(&cs->base, 0xf0000000); /* NOP packet */
         } else {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 20cfc86ebe0..d33c4c7132d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -50,14 +50,14 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
 {
     uint32_t tile_mode;
 
-    if (info->chip_class < SI) {
+    if (info->chip_class < GFX6) {
         surf->micro_tile_mode = 0;
         return;
     }
 
     tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
 
-    if (info->chip_class >= CIK)
+    if (info->chip_class >= GFX7)
         surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
     else
         surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
@@ -231,7 +231,7 @@ static void si_compute_cmask(const struct radeon_info *info,
 	if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
 		return;
 
-	assert(info->chip_class <= VI);
+	assert(info->chip_class <= GFX8);
 
 	switch (num_pipes) {
 	case 2:
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 293372cc26d..225cc01a33d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -269,14 +269,14 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     case CHIP_VERDE:
     case CHIP_OLAND:
     case CHIP_HAINAN:
-        ws->info.chip_class = SI;
+        ws->info.chip_class = GFX6;
         break;
     case CHIP_BONAIRE:
     case CHIP_KAVERI:
     case CHIP_KABINI:
     case CHIP_HAWAII:
     case CHIP_MULLINS:
-        ws->info.chip_class = CIK;
+        ws->info.chip_class = GFX7;
         break;
     }
 
@@ -542,18 +542,18 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
         return false;
     }
 
-    if (ws->info.chip_class == CIK) {
+    if (ws->info.chip_class == GFX7) {
         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
                                   ws->info.cik_macrotile_mode_array)) {
-            fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n");
+            fprintf(stderr, "radeon: Kernel 3.13 is required for Sea Islands support.\n");
             return false;
         }
     }
 
-    if (ws->info.chip_class >= SI) {
+    if (ws->info.chip_class >= GFX6) {
         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
                                   ws->info.si_tile_mode_array)) {
-            fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n");
+            fprintf(stderr, "radeon: Kernel 3.10 is required for Southern Islands support.\n");
             return false;
         }
     }
@@ -561,14 +561,14 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     /* Hawaii with old firmware needs type2 nop packet.
      * accel_working2 with value 3 indicates the new firmware.
      */
-    ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
+    ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= GFX6 ||
 				     (ws->info.family == CHIP_HAWAII &&
 				      ws->accel_working2 < 3);
     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
     ws->info.ib_start_alignment = 4096;
     ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
-    /* HTILE is broken with 1D tiling on old kernels and CIK. */
-    ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
+    /* HTILE is broken with 1D tiling on old kernels and GFX7. */
+    ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != GFX7 ||
                                              ws->info.drm_minor >= 38;
     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
     ws->info.has_bo_metadata = false;
@@ -579,15 +579,15 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.kernel_flushes_tc_l2_after_ib = true;
     /* Old kernels disallowed register writes via COPY_DATA
      * that are used for indirect compute dispatches. */
-    ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
-                                             (ws->info.chip_class == SI &&
+    ws->info.has_indirect_compute_dispatch = ws->info.chip_class == GFX7 ||
+                                             (ws->info.chip_class == GFX6 &&
                                               ws->info.drm_minor >= 45);
-    /* SI doesn't support unaligned loads. */
-    ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
+    /* GFX6 doesn't support unaligned loads. */
+    ws->info.has_unaligned_shader_loads = ws->info.chip_class == GFX7 &&
                                           ws->info.drm_minor >= 50;
     ws->info.has_sparse_vm_mappings = false;
-    /* 2D tiling on CIK is supported since DRM 2.35.0 */
-    ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
+    /* 2D tiling on GFX7 is supported since DRM 2.35.0 */
+    ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35;
     ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
     ws->info.max_alignment = 1024*1024;