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authorMarek Olšák <[email protected]>2016-01-30 01:52:58 +0100
committerMarek Olšák <[email protected]>2016-02-05 17:28:24 +0100
commit294ec530c9829aead97487b1feb06361ef97cc2d (patch)
tree68a200138a024ed0f9e1cab72bd41b1f2dafc523 /src/gallium/winsys/radeon
parent0f3556d308f155936c545ed8b9737c5e3f11a620 (diff)
gallium/radeon: just get num_tile_pipes from the winsys
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/winsys/radeon')
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3c8d5a7e20d..b97ccfd1679 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -392,6 +392,11 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
&ws->info.r600_gb_backend_map))
ws->info.r600_gb_backend_map_valid = TRUE;
+ } else {
+ ws->info.num_tile_pipes =
+ ws->info.chip_class >= EVERGREEN ?
+ 1 << (ws->info.r600_tiling_config & 0xf) :
+ 1 << ((ws->info.r600_tiling_config & 0xe) >> 1);
}
ws->info.has_virtual_memory = FALSE;