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authorHenri Verbeet <[email protected]>2011-01-18 20:43:56 +0100
committerHenri Verbeet <[email protected]>2011-01-18 20:57:04 +0100
commit9e964baaf34fedec385a750b97fd6684fc52584a (patch)
tree001856468f9638ce6445734c7d1125c342d9e267 /src/gallium/winsys/r600
parent7e2e8d09f78e326662bd275cac25a7b596b38965 (diff)
r600g: Kill trailing whitespace.
Diffstat (limited to 'src/gallium/winsys/r600')
-rw-r--r--src/gallium/winsys/r600/drm/bof.c2
-rw-r--r--src/gallium/winsys/r600/drm/radeon_bo.c4
-rw-r--r--src/gallium/winsys/r600/drm/radeon_pciid.c76
3 files changed, 41 insertions, 41 deletions
diff --git a/src/gallium/winsys/r600/drm/bof.c b/src/gallium/winsys/r600/drm/bof.c
index 0598cc6bc0f..5c923ad38d6 100644
--- a/src/gallium/winsys/r600/drm/bof.c
+++ b/src/gallium/winsys/r600/drm/bof.c
@@ -46,7 +46,7 @@ static int bof_entry_grow(bof_t *bof)
}
/*
- * object
+ * object
*/
bof_t *bof_object(void)
{
diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c
index 7e5f392efae..999de82646d 100644
--- a/src/gallium/winsys/r600/drm/radeon_bo.c
+++ b/src/gallium/winsys/r600/drm/radeon_bo.c
@@ -206,13 +206,13 @@ int radeon_bo_get_tiling_flags(struct radeon *radeon,
{
struct drm_radeon_gem_get_tiling args;
int ret;
-
+
args.handle = bo->handle;
ret = drmCommandWriteRead(radeon->fd, DRM_RADEON_GEM_GET_TILING,
&args, sizeof(args));
if (ret)
return ret;
-
+
*tiling_flags = args.tiling_flags;
*pitch = args.pitch;
return ret;
diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c b/src/gallium/winsys/r600/drm/radeon_pciid.c
index e2622abd468..06681791e57 100644
--- a/src/gallium/winsys/r600/drm/radeon_pciid.c
+++ b/src/gallium/winsys/r600/drm/radeon_pciid.c
@@ -40,29 +40,29 @@ struct pci_id radeon_pci_id[] = {
{0x1002, 0x3E54, CHIP_RV380},
{0x1002, 0x4136, CHIP_RS100},
{0x1002, 0x4137, CHIP_RS200},
- {0x1002, 0x4144, CHIP_R300},
- {0x1002, 0x4145, CHIP_R300},
- {0x1002, 0x4146, CHIP_R300},
- {0x1002, 0x4147, CHIP_R300},
- {0x1002, 0x4148, CHIP_R350},
- {0x1002, 0x4149, CHIP_R350},
- {0x1002, 0x414A, CHIP_R350},
- {0x1002, 0x414B, CHIP_R350},
- {0x1002, 0x4150, CHIP_RV350},
- {0x1002, 0x4151, CHIP_RV350},
- {0x1002, 0x4152, CHIP_RV350},
- {0x1002, 0x4153, CHIP_RV350},
- {0x1002, 0x4154, CHIP_RV350},
- {0x1002, 0x4155, CHIP_RV350},
- {0x1002, 0x4156, CHIP_RV350},
+ {0x1002, 0x4144, CHIP_R300},
+ {0x1002, 0x4145, CHIP_R300},
+ {0x1002, 0x4146, CHIP_R300},
+ {0x1002, 0x4147, CHIP_R300},
+ {0x1002, 0x4148, CHIP_R350},
+ {0x1002, 0x4149, CHIP_R350},
+ {0x1002, 0x414A, CHIP_R350},
+ {0x1002, 0x414B, CHIP_R350},
+ {0x1002, 0x4150, CHIP_RV350},
+ {0x1002, 0x4151, CHIP_RV350},
+ {0x1002, 0x4152, CHIP_RV350},
+ {0x1002, 0x4153, CHIP_RV350},
+ {0x1002, 0x4154, CHIP_RV350},
+ {0x1002, 0x4155, CHIP_RV350},
+ {0x1002, 0x4156, CHIP_RV350},
{0x1002, 0x4237, CHIP_RS200},
- {0x1002, 0x4242, CHIP_R200},
- {0x1002, 0x4243, CHIP_R200},
+ {0x1002, 0x4242, CHIP_R200},
+ {0x1002, 0x4243, CHIP_R200},
{0x1002, 0x4336, CHIP_RS100},
{0x1002, 0x4337, CHIP_RS200},
{0x1002, 0x4437, CHIP_RS200},
- {0x1002, 0x4966, CHIP_RV250},
- {0x1002, 0x4967, CHIP_RV250},
+ {0x1002, 0x4966, CHIP_RV250},
+ {0x1002, 0x4967, CHIP_RV250},
{0x1002, 0x4A48, CHIP_R420},
{0x1002, 0x4A49, CHIP_R420},
{0x1002, 0x4A4A, CHIP_R420},
@@ -85,14 +85,14 @@ struct pci_id radeon_pci_id[] = {
{0x1002, 0x4C64, CHIP_RV250},
{0x1002, 0x4C66, CHIP_RV250},
{0x1002, 0x4C67, CHIP_RV250},
- {0x1002, 0x4E44, CHIP_R300},
- {0x1002, 0x4E45, CHIP_R300},
- {0x1002, 0x4E46, CHIP_R300},
- {0x1002, 0x4E47, CHIP_R300},
- {0x1002, 0x4E48, CHIP_R350},
- {0x1002, 0x4E49, CHIP_R350},
- {0x1002, 0x4E4A, CHIP_R350},
- {0x1002, 0x4E4B, CHIP_R350},
+ {0x1002, 0x4E44, CHIP_R300},
+ {0x1002, 0x4E45, CHIP_R300},
+ {0x1002, 0x4E46, CHIP_R300},
+ {0x1002, 0x4E47, CHIP_R300},
+ {0x1002, 0x4E48, CHIP_R350},
+ {0x1002, 0x4E49, CHIP_R350},
+ {0x1002, 0x4E4A, CHIP_R350},
+ {0x1002, 0x4E4B, CHIP_R350},
{0x1002, 0x4E50, CHIP_RV350},
{0x1002, 0x4E51, CHIP_RV350},
{0x1002, 0x4E52, CHIP_RV350},
@@ -103,13 +103,13 @@ struct pci_id radeon_pci_id[] = {
{0x1002, 0x5145, CHIP_R100},
{0x1002, 0x5146, CHIP_R100},
{0x1002, 0x5147, CHIP_R100},
- {0x1002, 0x5148, CHIP_R200},
- {0x1002, 0x514C, CHIP_R200},
- {0x1002, 0x514D, CHIP_R200},
- {0x1002, 0x5157, CHIP_RV200},
- {0x1002, 0x5158, CHIP_RV200},
- {0x1002, 0x5159, CHIP_RV100},
- {0x1002, 0x515A, CHIP_RV100},
+ {0x1002, 0x5148, CHIP_R200},
+ {0x1002, 0x514C, CHIP_R200},
+ {0x1002, 0x514D, CHIP_R200},
+ {0x1002, 0x5157, CHIP_RV200},
+ {0x1002, 0x5158, CHIP_RV200},
+ {0x1002, 0x5159, CHIP_RV100},
+ {0x1002, 0x515A, CHIP_RV100},
{0x1002, 0x515E, CHIP_RV100},
{0x1002, 0x5460, CHIP_RV380},
{0x1002, 0x5462, CHIP_RV380},
@@ -138,10 +138,10 @@ struct pci_id radeon_pci_id[] = {
{0x1002, 0x5955, CHIP_RS480},
{0x1002, 0x5974, CHIP_RS480},
{0x1002, 0x5975, CHIP_RS480},
- {0x1002, 0x5960, CHIP_RV280},
- {0x1002, 0x5961, CHIP_RV280},
- {0x1002, 0x5962, CHIP_RV280},
- {0x1002, 0x5964, CHIP_RV280},
+ {0x1002, 0x5960, CHIP_RV280},
+ {0x1002, 0x5961, CHIP_RV280},
+ {0x1002, 0x5962, CHIP_RV280},
+ {0x1002, 0x5964, CHIP_RV280},
{0x1002, 0x5965, CHIP_RV280},
{0x1002, 0x5969, CHIP_RV100},
{0x1002, 0x5a41, CHIP_RS400},