diff options
| author | Marek Olšák <[email protected]> | 2017-02-15 18:22:27 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-02-18 01:22:08 +0100 |
| commit | 6b73aafceb1eb8e81754e2f349826994de678466 (patch) | |
| tree | 8867b645888363ea28c3e1f87ac270ead32403ca /src/gallium/winsys/amdgpu | |
| parent | 620aded541a5b81df74575888754094fea2f2ae2 (diff) | |
radeonsi: use a clever alignment for constant buffer uploads
This results in a very tiny decrease in lgkm wait cycles.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index db0087c094e..6511c4855d8 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -345,6 +345,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd) ws->info.has_userptr = true; ws->info.num_render_backends = ws->amdinfo.rb_pipes; ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq; + ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo); ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7); ws->info.has_virtual_memory = true; |