From 6b73aafceb1eb8e81754e2f349826994de678466 Mon Sep 17 00:00:00 2001 From: Marek Olšák Date: Wed, 15 Feb 2017 18:22:27 +0100 Subject: radeonsi: use a clever alignment for constant buffer uploads MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This results in a very tiny decrease in lgkm wait cycles. Reviewed-by: Nicolai Hähnle --- src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/gallium/winsys/amdgpu') diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index db0087c094e..6511c4855d8 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -345,6 +345,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd) ws->info.has_userptr = true; ws->info.num_render_backends = ws->amdinfo.rb_pipes; ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq; + ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo); ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7); ws->info.has_virtual_memory = true; -- cgit v1.2.3