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authorBen Widawsky <[email protected]>2016-04-21 20:14:58 -0700
committerBen Widawsky <[email protected]>2016-04-21 20:14:58 -0700
commit6a0d036483caf87d43ebe2edd1905873446c9589 (patch)
tree7ff5af3ac27d8cb5c07893a3fc6bc1d1773b8c79 /src/gallium/winsys/amdgpu/drm
parentc3b88cc2c15f19e748c9c406e9ab053975adab7e (diff)
i965: Always use Y-tiled buffers on SKL+
Starting with Skylake, the display engine is capable of scanning out from Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency. This also has the added benefit of being able to fast clear the winsys buffer. Note that the buffer allocation done for mipmaps will already never allocate an X-tiled buffer for GEN9. This has an almost universal positive impact on benchmarks, some improving by as much as 20%. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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