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authorMarek Olšák <[email protected]>2016-05-01 13:56:01 +0200
committerMarek Olšák <[email protected]>2016-05-02 22:49:25 +0200
commitc8aac4fc0dce61a8061bccb8d63a94f1eacd5348 (patch)
treec2d566261dd462bba18e6524c578577f5952c838 /src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
parentdc970c4f4e03e17e32132734c1707d845ab610c9 (diff)
winsys/amdgpu: pass PIPE_CONFIG to addrlib on texture import
This hasn't been needed, but I think we should set it. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/winsys/amdgpu/drm/amdgpu_bo.c')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_bo.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 4ab85ff0721..37a41c03540 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -408,6 +408,7 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
md->microtile = RADEON_LAYOUT_TILED;
+ md->pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));