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authorNicolai Hähnle <nicolai.haehnle@amd.com>2017-05-11 10:19:26 +0200
committerNicolai Hähnle <nicolai.haehnle@amd.com>2017-05-18 11:48:52 +0200
commitde9dd4f9f1bb5984c554d0acf7d2592951ecc53f (patch)
treef8d28389f075b8a7e7b14be41330f6233d1375dd /src/gallium/drivers
parent4d6e75776dced684dee0a78c5b70cd96376e84a8 (diff)
ac/radeonsi: move struct radeon_info to ac_gpu_info.h
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/radeon/radeon_winsys.h62
1 files changed, 1 insertions, 61 deletions
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 1d94b88ef4d..45ad561e236 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -28,7 +28,7 @@
#include "pipebuffer/pb_buffer.h"
-#include "amd/common/amd_family.h"
+#include "amd/common/ac_gpu_info.h"
#include "amd/common/ac_surface.h"
#define RADEON_FLUSH_ASYNC (1 << 0)
@@ -176,66 +176,6 @@ struct radeon_winsys_cs {
uint64_t used_gart;
};
-struct radeon_info {
- /* PCI info: domain:bus:dev:func */
- uint32_t pci_domain;
- uint32_t pci_bus;
- uint32_t pci_dev;
- uint32_t pci_func;
-
- /* Device info. */
- uint32_t pci_id;
- enum radeon_family family;
- enum chip_class chip_class;
- uint32_t gart_page_size;
- uint64_t gart_size;
- uint64_t vram_size;
- uint64_t vram_vis_size;
- uint64_t max_alloc_size;
- uint32_t min_alloc_size;
- bool has_dedicated_vram;
- bool has_virtual_memory;
- bool gfx_ib_pad_with_type2;
- bool has_sdma;
- bool has_uvd;
- uint32_t uvd_fw_version;
- uint32_t vce_fw_version;
- uint32_t me_fw_version;
- uint32_t pfp_fw_version;
- uint32_t ce_fw_version;
- uint32_t vce_harvest_config;
- uint32_t clock_crystal_freq;
- uint32_t tcc_cache_line_size;
-
- /* Kernel info. */
- uint32_t drm_major; /* version */
- uint32_t drm_minor;
- uint32_t drm_patchlevel;
- bool has_userptr;
-
- /* Shader cores. */
- uint32_t r600_max_quad_pipes; /* wave size / 16 */
- uint32_t max_shader_clock;
- uint32_t num_good_compute_units;
- uint32_t max_se; /* shader engines */
- uint32_t max_sh_per_se; /* shader arrays per shader engine */
-
- /* Render backends (color + depth blocks). */
- uint32_t r300_num_gb_pipes;
- uint32_t r300_num_z_pipes;
- uint32_t r600_gb_backend_map; /* R600 harvest config */
- bool r600_gb_backend_map_valid;
- uint32_t r600_num_banks;
- uint32_t num_render_backends;
- uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
- uint32_t pipe_interleave_bytes;
- uint32_t enabled_rb_mask; /* GCN harvest config */
-
- /* Tile modes. */
- uint32_t si_tile_mode_array[32];
- uint32_t cik_macrotile_mode_array[16];
-};
-
/* Tiling info for display code, DRI sharing, and other data. */
struct radeon_bo_metadata {
/* Tiling flags describing the texture layout for display code