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authorIlia Mirkin <[email protected]>2020-07-05 01:58:01 -0400
committerMarge Bot <[email protected]>2020-07-06 23:57:51 +0000
commit836d41d77265a2d2ca42bdbfd25de07b9bb134c9 (patch)
tree3723070b1f477cd342fd9419872f1b6ae594fde3 /src/gallium/drivers
parentf6aa0719cfaf10299d2c5112ddfbee91b4b732a9 (diff)
ir3: use empirical size for params as used by the shader
For example only some UCPs may be used by the shader, triggering asserts that too many consts are being uploaded. While we're at it, also fix the const size when loading UCPs, since otherwise it doesn't correspond to what the shader is actually using. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5752>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_const.h15
1 files changed, 8 insertions, 7 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_const.h b/src/gallium/drivers/freedreno/ir3/ir3_const.h
index 1bcd53b66b0..1bb19b63cea 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_const.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_const.h
@@ -451,11 +451,6 @@ ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
info->index_bias : info->start,
[IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
};
- /* if no user-clip-planes, we don't need to emit the
- * entire thing:
- */
- uint32_t vertex_params_size = 4;
-
if (v->key.ucp_enables) {
struct pipe_clip_state *ucp = &ctx->ucp;
unsigned pos = IR3_DP_UCP0_X;
@@ -465,10 +460,16 @@ ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
pos++;
}
}
- vertex_params_size = ARRAY_SIZE(vertex_params);
}
- vertex_params_size = MAX2(vertex_params_size, const_state->num_driver_params);
+ /* Only emit as many params as needed, i.e. up to the highest enabled UCP
+ * plane. However a binning pass may drop even some of these, so limit to
+ * program max.
+ */
+ const uint32_t vertex_params_size = MIN2(
+ const_state->num_driver_params,
+ (v->constlen - offset) * 4);
+ assert(vertex_params_size <= IR3_DP_VS_COUNT);
bool needs_vtxid_base =
ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);