diff options
| author | Ilia Mirkin <[email protected]> | 2016-01-15 17:12:27 -0500 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2016-01-16 00:10:56 -0500 |
| commit | 32a9fe013b9fbc93d9045341cb7cbe13231523fb (patch) | |
| tree | 34eaf40e0773af010bb5f8a02f477cca5622f9f1 /src/gallium/drivers | |
| parent | e5fefe49f2f86b5125da87c44fe855fd6f3424fc (diff) | |
nv50/ir: add saturate support on ex2
Signed-off-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 5 | ||||
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp index c126c085daf..bc8354deba1 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp @@ -1463,6 +1463,7 @@ CodeEmitterNV50::emitSFnOp(const Instruction *i, uint8_t subOp) if (i->encSize == 4) { assert(i->op == OP_RCP); + assert(!i->saturate); code[0] |= i->src(0).mod.abs() << 15; code[0] |= i->src(0).mod.neg() << 22; emitForm_MUL(i); @@ -1470,6 +1471,10 @@ CodeEmitterNV50::emitSFnOp(const Instruction *i, uint8_t subOp) code[1] = subOp << 29; code[1] |= i->src(0).mod.abs() << 20; code[1] |= i->src(0).mod.neg() << 26; + if (i->saturate) { + assert(subOp == 6 && i->op == OP_EX2); + code[1] |= 1 << 27; + } emitForm_MAD(i); } } diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp index 101082e7491..2c4d7f53d60 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp @@ -99,6 +99,7 @@ static const struct opProperties _initProps[] = { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x1, 0x1, 0x0 }, { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, + { OP_EX2, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0, 0x0, 0x0 }, { OP_LG2, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, { OP_RCP, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, { OP_RSQ, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, |