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authorRob Clark <[email protected]>2018-04-01 11:26:01 -0400
committerRob Clark <[email protected]>2018-04-01 11:26:01 -0400
commit2f175bfe5d8ca59a8a68b6d6d072cd7bf2f8baa9 (patch)
tree7dbae1e07fca44fdfc2929d13fb7b5a35e0185ee /src/gallium/drivers
parent1866f76f7bc3ec54b4e91eb7d329b2e6f7b6277c (diff)
freedreno/a5xx: don't align height for PIPE_BUFFER
Buffers can be large, so we probably don't want to make them all 32x bigger. But they can't be rendered to (at least in GL) so we don't need this workaround to prevent page faults on mem<->gmem. Cc: "18.0" <[email protected]> Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_resource.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_resource.c b/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
index 84fa64cec84..71bcc381528 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_resource.c
@@ -81,7 +81,7 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma
* The pitch is already sufficiently aligned, but height
* may not be:
*/
- if (level == prsc->last_level)
+ if ((level == prsc->last_level) && (prsc->target != PIPE_BUFFER))
aligned_height = align(aligned_height, 32);
}