diff options
| author | Marek Olšák <[email protected]> | 2017-02-09 02:17:37 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-02-10 11:27:50 +0100 |
| commit | 1a392a43779b4e5650eed54cd149cea9a6b0a2a0 (patch) | |
| tree | 63d9787780eaa5ff91cf9127d5ea7a046edd42ea /src/gallium/drivers | |
| parent | 4c288c73ead458cd8eed4c622d8a435a00d04442 (diff) | |
radeonsi: move CP_DMA_ALIGNMENT definition
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_cp_dma.c | 18 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 2 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index 540f946d5a2..9fa3ccb6c27 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -28,10 +28,8 @@ #include "sid.h" #include "radeon/r600_cs.h" -/* Alignment for optimal performance. */ -#define CP_DMA_ALIGNMENT 32 /* The max number of bytes to copy per packet. */ -#define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - CP_DMA_ALIGNMENT) +#define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - SI_CPDMA_ALIGNMENT) /* Set this if you want the ME to wait until CP DMA is done. * It should be set on the last CP DMA packet. */ @@ -267,9 +265,9 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, { uint64_t va; unsigned dma_flags = 0; - unsigned scratch_size = CP_DMA_ALIGNMENT * 2; + unsigned scratch_size = SI_CPDMA_ALIGNMENT * 2; - assert(size < CP_DMA_ALIGNMENT); + assert(size < SI_CPDMA_ALIGNMENT); /* Use the scratch buffer as the dummy buffer. The 3D engine should be * idle at this point. @@ -291,7 +289,7 @@ static void si_cp_dma_realign_engine(struct si_context *sctx, unsigned size, is_first, &dma_flags); va = sctx->scratch_buffer->gpu_address; - si_emit_cp_dma(sctx, va, va + CP_DMA_ALIGNMENT, size, dma_flags, + si_emit_cp_dma(sctx, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags, R600_COHERENCY_SHADER); } @@ -333,15 +331,15 @@ void si_copy_buffer(struct si_context *sctx, * just to align the internal counter. Otherwise, the DMA engine * would slow down by an order of magnitude for following copies. */ - if (size % CP_DMA_ALIGNMENT) - realign_size = CP_DMA_ALIGNMENT - (size % CP_DMA_ALIGNMENT); + if (size % SI_CPDMA_ALIGNMENT) + realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT); /* If the copy begins unaligned, we must start copying from the next * aligned block and the skipped part should be copied after everything * else has been copied. Only the src alignment matters, not dst. */ - if (src_offset % CP_DMA_ALIGNMENT) { - skipped_size = CP_DMA_ALIGNMENT - (src_offset % CP_DMA_ALIGNMENT); + if (src_offset % SI_CPDMA_ALIGNMENT) { + skipped_size = SI_CPDMA_ALIGNMENT - (src_offset % SI_CPDMA_ALIGNMENT); /* The main part will be skipped if the size is too small. */ skipped_size = MIN2(skipped_size, size); size -= skipped_size; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index ffd1bce812d..fb24babe61f 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -41,6 +41,8 @@ #define SI_RESTART_INDEX_UNKNOWN INT_MIN #define SI_NUM_SMOOTH_AA_SAMPLES 8 #define SI_GS_PER_ES 128 +/* Alignment for optimal CP DMA performance. */ +#define SI_CPDMA_ALIGNMENT 32 /* Instruction cache. */ #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0) |