diff options
| author | Eric Anholt <[email protected]> | 2015-01-10 15:59:56 +1300 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2015-01-11 08:57:24 +1300 |
| commit | 355156d2f75ffb5fae90dd6583ae3cf465ba40b4 (patch) | |
| tree | 59643c4204e3f666e51ee91c69a0daf48242c113 /src/gallium/drivers/vc4/vc4_register_allocate.c | |
| parent | a8e14c293b19a2d298f91f283d6b6839f36fb518 (diff) | |
vc4: Avoid the save/restore of r3 for raddr conflicts, just use ra31.
Turns out this was harmful in code quality:
total instructions in shared programs: 39487 -> 38845 (-1.63%)
instructions in affected programs: 22522 -> 21880 (-2.85%)
This costs us yet another register, which is painful since it means more
programs might fail to compile). However, the alternative was causing us
trouble where we'd save/restore r3 while it contained a MIN-ed direct
texture offset, causing the kernel to fail to validate our shaders (such
as in GLB2.7).
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_register_allocate.c')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_register_allocate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c b/src/gallium/drivers/vc4/vc4_register_allocate.c index 9eae7fca758..efd9d51eaa0 100644 --- a/src/gallium/drivers/vc4/vc4_register_allocate.c +++ b/src/gallium/drivers/vc4/vc4_register_allocate.c @@ -117,10 +117,10 @@ vc4_alloc_reg_set(struct vc4_context *vc4) vc4->reg_class_any = ra_alloc_reg_class(vc4->regs); for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) { - /* Reserve rb31 for spilling fixup_raddr_conflict() in + /* Reserve ra31/rb31 for spilling fixup_raddr_conflict() in * vc4_qpu_emit.c */ - if (vc4_regs[i].mux == QPU_MUX_B && vc4_regs[i].addr == 31) + if (vc4_regs[i].addr == 31) continue; /* R4 can't be written as a general purpose register. (it's |