vc4: Reuse QPU disasm's cond flags in QIR.

In the process, this made me flatten out the "%s%s%s%s" fprintf arguments.

1 files changed, 38 insertions, 13 deletions

diff --git a/src/gallium/drivers/vc4/vc4_qpu_disasm.c b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
index c46fd1a0e3f..673c1bba092 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_disasm.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
@@ -213,7 +213,7 @@ static const char *qpu_pack_a[] = {
         [QPU_PACK_A_8D_SAT] = ".8d.sat",
 };
 
-static const char *qpu_condflags[] = {
+static const char *qpu_cond[] = {
         [QPU_COND_NEVER] = ".never",
         [QPU_COND_ALWAYS] = "",
         [QPU_COND_ZS] = ".zs",
@@ -264,6 +264,12 @@ vc4_qpu_disasm_unpack(FILE *out, uint32_t unpack)
                 fprintf(out, ".%s", DESC(qpu_unpack, unpack));
 }
 
+void
+vc4_qpu_disasm_cond(FILE *out, uint32_t cond)
+{
+        fprintf(out, "%s", DESC(qpu_cond, cond));
+}
+
 static void
 print_alu_dst(uint64_t inst, bool is_mul)
 {
@@ -337,11 +343,18 @@ print_add_op(uint64_t inst)
                        QPU_GET_FIELD(inst, QPU_ADD_A) ==
                        QPU_GET_FIELD(inst, QPU_ADD_B));
 
-        fprintf(stderr, "%s%s%s ",
-                is_mov ? "mov" : DESC(qpu_add_opcodes, op_add),
-                ((inst & QPU_SF) && op_add != QPU_A_NOP) ? ".sf" : "",
-                op_add != QPU_A_NOP ? DESC(qpu_condflags, cond) : "");
+        if (is_mov)
+                fprintf(stderr, "mov");
+        else
+                fprintf(stderr, DESC(qpu_add_opcodes, op_add));
+
+        if ((inst & QPU_SF) && op_add != QPU_A_NOP)
+                fprintf(stderr, ".sf");
 
+        if (op_add != QPU_A_NOP)
+                vc4_qpu_disasm_cond(stderr, cond);
+
+        fprintf(stderr, " ");
         print_alu_dst(inst, false);
         fprintf(stderr, ", ");
 
@@ -364,11 +377,18 @@ print_mul_op(uint64_t inst)
                        QPU_GET_FIELD(inst, QPU_MUL_A) ==
                        QPU_GET_FIELD(inst, QPU_MUL_B));
 
-        fprintf(stderr, "%s%s%s ",
-                is_mov ? "mov" : DESC(qpu_mul_opcodes, op_mul),
-                ((inst & QPU_SF) && op_add == QPU_A_NOP) ? ".sf" : "",
-                op_mul != QPU_M_NOP ? DESC(qpu_condflags, cond) : "");
+        if (is_mov)
+                fprintf(stderr, "mov");
+        else
+                fprintf(stderr, "%s", DESC(qpu_mul_opcodes, op_mul));
 
+        if ((inst & QPU_SF) && op_add == QPU_A_NOP)
+                fprintf(stderr, ".sf");
+
+        if (op_mul != QPU_M_NOP)
+                vc4_qpu_disasm_cond(stderr, cond);
+
+        fprintf(stderr, " ");
         print_alu_dst(inst, true);
         fprintf(stderr, ", ");
 
@@ -390,12 +410,17 @@ print_load_imm(uint64_t inst)
         uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL);
 
         fprintf(stderr, "load_imm ");
+
         print_alu_dst(inst, false);
-        fprintf(stderr, "%s, ", (waddr_add != QPU_W_NOP ?
-                                 DESC(qpu_condflags, cond_add) : ""));
+        if (waddr_add != QPU_W_NOP)
+                vc4_qpu_disasm_cond(stderr, cond_add);
+        fprintf(stderr, ", ");
+
         print_alu_dst(inst, true);
-        fprintf(stderr, "%s, ", (waddr_mul != QPU_W_NOP ?
-                                 DESC(qpu_condflags, cond_mul) : ""));
+        if (waddr_mul != QPU_W_NOP)
+                vc4_qpu_disasm_cond(stderr, cond_mul);
+        fprintf(stderr, ", ");
+
         fprintf(stderr, "0x%08x (%f)", imm, uif(imm));
 }